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Interfacing Cypress MoBL(R) Dual-Port to Intel(R) PXA272 Embedded Processor
Introduction
The PXA272 Embedded Processor of the Intel(R) PCA processor family is an integrated system-on-a-chip microprocessor for high performance, dynamic and low-power portable handheld and handset devices. The Intel PXA272 processor includes a memory interface that gives designers more flexibility as it supports a variety of external memory types. CYDM256A16 is an asynchronous MoBL(R) Dual-Port memory from Cypress Semiconductor. It has a 256-Kbit shared memory array with two 16-bit data buses. The shared memory structure allows independent access from both ports to 32K address locations. The device is available in -35 and -55 speed grades in both commercial and industrial temperature ranges. Internal arbitration logic is also available to decide which port gets access when both ports try to access the same memory location at the same time. The MoBL Dual-Port can act as an interconnect between two processing elements that share data while operating at different speeds. This application note describes how to interface the CYDM256A16 to the Intel PXA272. Table 1. PXA272 & CYDM256A16 Signal Equivalents (continued) PXA272 Signal (I/O) External Devices External Devices I O CYDM256A16 Signal (I/O) ODR[4:0] IRR[1:0] M/S O I I Function Output Drive Register Input Read Register Master/Slave Select: pulled up to VCC
Layout Guidelines
Figure 1 below shows the physical wiring between the PXA272 processor and the MoBL Dual-Port CYDM256A16. Either port of the MoBL Dual-Port may be used. Table 2 shows the list of unused PXA272 EMI pins.
DQ[15:0] A[14:0] CE OE R/W UB LB INT BUSY SFEN M/S IRR ODR Cypress MoBL Dual-Port CYDM256A16 MD[15:0] MA[14:0] CSx OE WE DQM[1] DQM[0] GPIO RDY GPIO
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External Memory Interface (EMI)
The Intel PXA272's External Memory Interface is a 16/32-bit interface and it can be configured to gluelessly interface to Cypress low-power MoBL Dual-Ports. The Cypress MoBL Dual-Port CYDM256A16 has a standard asynchronous SRAM interface. Table 1 lists the signal connections between Intel PXA272 and Cypress MoBL Dual-Port CYDM256A16. Table 1. PXA272 & CYDM256A16 Signal Equivalents PXA272 Signal (I/O) CSx WE OE MA[14:0] MD[15:0] DQM[1] DQM[0] RDY GPIOx GPIOx O O O O I/O O O I I O CYDM256A16 Signal (I/O) CE R/W OE A[14:0] DQ[15:0] UB LB BUSY INT SFEN I I I I I/O I I I/O O I
Vcc Ext. Inputs Ext. Outputs
Intel Embedded Processor PXA272
Figure 1. Wiring Diagram of PXA272 to CYDM256A16 Function Chip select Write enable Output enable Address Data Upper byte enable Lower byte enable Busy Signal Mailbox Interrupt Special Function enable MA[25:15] CLK NC NC Table 2. Unused Intel PXA272 Signals
Voltage Compatibility
Cypress MoBL Dual-Ports have operating voltages of 1.8V, 2.5V, and 3.0V, while the Intel PXA272 supports 1.8V, 2.5V and 3.3V I/O supply voltages. Thus, the Cypress MoBL Dual-Ports are compatible with the Intel processor PXA272 when both devices operate at the same voltage.
Cypress Semiconductor Corporation
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3901 North First Street
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San Jose, CA 95134 * 408-943-2600 Revised March 31, 2005
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Interfacing Cypress MoBLTM Dual-Port to Intel PXA272 Embedded Processor
PXA272 Register Settings
In order to properly interface the PXA272 to the Cypress MoBL Dual-Port, the MSCx register of the processor needs to be configured, while the rest of the registers can be left in their default settings. Table 3 shows the recommended MSCx register setting, assuming the PXA272 processor is running at 520 MHz and connected to the CYDM256A16-55. The same analysis can be used to interface the processor to Dual-Ports with the -35 speed grade. Table 3. MSCx Register Settings Field RTx RBW RDF RDN RRR RBUFF Value 001b 1b 1111b 1111b 101b 0b Description Type of memory: SRAM Data bus width: 16 bits ROM/SRAM delay first access: 30* Clock pulse equivalent of processor ROM/SRAM delay next access: 30* clock pulse equivalent of processor ROM/SRAM Recovery Time Fast/Slow device: Slow Device
Read Operation With an internal reference clock of 520 MHz (1.923-ns clock period), the register settings required to set up proper read operations are shown in Table 3. RDF (ROM Delay First access), which defines the number of wait states inserted in a read cycle, needs to be 30 times the REF_CLK clock cycle. This essentially extends the chip select enable duration of a read cycle to 30 x REF_CLK = 57.7ns. Figure 2 shows the timing details of a read operation between the PXA272 and MoBL Dual-Port. To initiate a read operation, the shortest read cycle needs to be at least tRC. The processor will also need to wait for the maximum of tAA, tABE and tACE for the data to propagate back from the MoBL Dual-Port. The CYDM256A16-55 MoBL Dual-Port has a tRC= 55 ns, tAA = 45ns and tABE = 45 ns. Read access time for the SRAM controller is configured through the RDF field of MSCx register. Referring to the Intel documentation: (RDFx+2)*(Time period of processor clock) > Read Cycle time of the MoBL Dual-Port. => RDFx > ((Read Cycle Time of MoBL Dual-Port/Time period of processor clock) - 2. => RDFx > (55ns/1.923) - 2 = 28.6 - 2 = 26.6. => RDFx > 26.6 Considering the worst case, the decoded value of RDF should be set to 30 for extra timing margin (RDF="1111"). Subsequent read operation: Before starting a subsequent MoBL Dual-Port read, the processor should wait for at least tHZCE = 20ns (max). To achieve this, we need to set the RRRx (ROM/SRAM recovery time) field of MSCx register. Referring to the Intel documentation: tOFF > (RRRx*2+1)*Processor Clock Period.
Timing Considerations
This section of the application note provides a sample timing analysis of read and write operations with the PXA272 processor and MoBL Dual-Port CYDM256A16-55. Assume that the system clock of the processor runs at the maximum frequency of 520 MHz. Please note that the register setting may vary depending on the speed of the desired memory as well as the system clock frequency (refer to PXA27x Processor Family Developers Manual for detail).
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tCLK tRC[1] RDFx X tCLK[2]
Processor Signal CSx
MoBL Dual-Port Signals CE
A[14:0] MD[14:0] OE OE DQ[15:0] MD[15:0] UB/LB DQM[1:0] R/W WE Figure 2. Read Cycle
Notes: 1. Required by the MoBL Dual-Port for proper read. 2. Provided by the Processor.
RRRx X tCLK[2] RDFx X tCLK[2] tAA[1] tSD[1] F6[2] F7[2]
tHZCE[1]
2
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Interfacing Cypress MoBLTM Dual-Port to Intel PXA272 Embedded Processor
=> RRRx > ((tOFF/Processor Clock Period) - 1)/2 => RRRx > ((20/1.923) - 1)/2 = 4.700 Considering the worst case, the decoded value of RRR should be set to 5 for extra timing margin (RRR="101"). Write Operation Figure 3 shows the timing detail of a write operation between the PXA272 processor and the MoBL Dual-Port. In order to write into the MoBL Dual-Port, the minimum write cycle needs to be at least tWC, while tAW, tSD, tHD, tSA, tHA and tSCE also need to be satisfied. Since tSA = tHD = tHA = 0, these parameters should always be satisfied. With tWC= 55 ns and tAW = tSCE = 45 ns, the processor has to assert the write cycle for at least 55 ns for a correct write operation. The write cycle time for the SRAM controller is configured through the RDNx (ROM Delay Next access) field of MSCx register. According to Intel documentation: RDNx + 1 = number of CLK_MEMs WE is asserted for write access. => RDNx > (Write Cycle Time/ Time period of clock) - 1. => RDNx > (55 ns/1.923 ns) - 1 = 28.6 - 1 = 27.6. Considering the worst case, the decoded value of RDN should be set to 30 for extra timing margin (RDN="1111"). Data Bus Switching For CYDM256A16, tHD = 0 ns. Before starting the next MoBL Dual-Port write, the processor should wait for at least tHD. Since MoBL Dual-Ports do not support burst mode, timing will always be satisfied by the processor if the MSCx register is configured with the values listed in Table 3. Processor Signal CSx A[14:0] MA[14:0] OE OE DQ[15:0] MD[15:0] UB/LB DQM[1:0] R/W WE MoBL Dual-Port Signal CE
Configuring the Memory Controller for PXA272
As discussed above, the memory controller must be configured to interface to the MoBL Dual-Port. Apart from the timing parameters, the data width and type of memory are also configured in the MSCx register. According to Table 3, using CS1, the upper 16 bits of the MSC0 (address 0x4800008) is set to "0101-1111-1111-1001". The memory space of the PXA272 processor is divided into 6 slots: CS[5:0]. The MoBl Dual-Port can connect to any of the chip selects. Table 4 shows the memory address space for each memory slot. Table 4. Address Space of PXA272 Processor Chip Select CS0 CS1-CS5 Size Function
32 MB Memory space for async. device 64 MB Memory space for async. device
Table 5 shows the timing parameter values required by the MoBL Dual-Port and the ones provided by the Intel PXA272 processor with the memory controller configuration described above.
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tCLK tWC[1] RDNx X tCLK[2]
RRRx X tCLK[2]
tSD[2]
tSD[1]
tHD[1] tHD[2]
Figure 3. Write Cycle
3
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Interfacing Cypress MoBLTM Dual-Port to Intel PXA272 Embedded Processor
Table 5. Timing Compatibility Table after Configuration Operation Read Read Read Read Read Read Read Write Write Write Write Write Write Write Parameter tRC tSA tOHA tACE tDOE tHZCE tABE tWC tHA tSA tSCE tAW tSD tHD Dual-Port CYDM16A256 55ns 0ns 5ns 55ns 30ns 20ns 55ns 55ns 0ns 0ns 25ns 45ns 30ns 0ns RRRx= "101" RDNx= "1111" RRRx= "101" RDFx= "1111" RDNx= "1111" RDFx= "1111" Relation RDFx= "1111" Processor PXA272 57.9 ns Always satisfied Always satisfied 57.9 ns Always satisfied 25 ns 57.9 ns 57.9 ns Always satisfied Always satisfied 25 ns 57.9 ns Always satisfied Always satisfied
Conclusion
Systems using a Intel PXA272 processor can easily benefit from the performance and flexibility of a Cypress Dual-Port. As one of the industry's lowest power Dual-Ports, designing in the Cypress MoBL Dual-Port allows the customer to interconnect multiple processors in a system, where power is the most important concern, without having to compromise with performance. As this application note has shown, the Intel PXA272 can interface to the Cypress MoBL Dual-Port seamlessly. For further information, please visit the Cypress web site at www.cypress.com. The web site also provides the latest data sheets, models, and any related documentation.
References
1. Cypress Semiconductor, CYDM256A16, CYDM128A16, CYDM064A16, CYDM128A08, CYDM064A08 1.8V, 2.5V, 3.3V 4K/8K/16K x16 and 8K/16K x8 MoBL(R) Dual-Port Static RAM Data sheet, January 2005. 2. Intel Inc., PXA272 Processor Design Guide, Literature Number 280000101.pdf. 3. Intel inc., PXA27x Processor Family Developers Manual 2800002.pdf.
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Intel is a registered trademark of Intel Corporation. MoBL is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
AN5035 approved kktvmp 3/31/05
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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